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清华—微电子类系列英文教材
数字集成电路——设计透视（影印版）（第2版）Digital Integrated Circuits A Design Perspective(Senond Edition)  |
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￥68.00(以下报价瞬息万变,建议您点击全部站点比对) | | |通过以下方式购买,或许更便宜: |
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【作 者】 Jan M.Rabaey
【开 本】16 【版 次】0次
【分 类】 计算机书店>>电路设计
【页 数】
761
【字 数】
0
【日 期】
2004年4月
【装 帧】
简装
【出版社】
清华大学出版社
【ISBN】
0
【关注程度】已有2006人关注该图书
【版本状态】『全图版』
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我要购书网的承诺：本网上购书中心所出售的"数字集成电路——设计透视（影印版）（第2版）Digital Integrated Circuits A Design Perspective(Senond Edition)"图书保证正版，您在本购书中心享有收到图书七天内无条件退货！收到商品15日之内换货的待遇！
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换货规定：从本购书中心所购买"数字集成电路——设计透视（影印版）（第2版）Digital Integrated Circuits A Design Perspective(Senond Edition)"图书如有质量问题(字迹模糊/缺页/倒装/开线/开胶/折页/封皮破损/缺少随书赠品),可在收到商品15日之内换货
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| 本书的特点主要包括： (1)将数字集成电路设计中电路与系统的视角统一起来，在系统深入地介绍了深亚微米条件下半导体器件的知识和最基本的反相器后，作者逐渐将这些基础知识引入到更加复杂的模块，比如门、寄存器、控制器、加法器、乘法器和存储器等。在深亚微米的设计条件下，设计者不仅仅需要考虑整个系统的设计问题，还要随时警惕在电路级——比如器件和连线所带来的问题。 (2)本书是第一本将数字集成电路设计问题集中在深亚微米条件下的参考书，并且提供了一个深亚微米条件下的简单晶体管模型。另外针对深亚微米条件下设计人员所面对的新挑战，例如互连线问题、信号完整性问题、时钟分布问题、功耗问题等，全书都做了非常详细的论述。 (3)书中的内容紧扣当今数字集成电路设计的核心问题，并通过大量的设计实例向读者介绍了最新的设计技术和工程发展现状与趋势。 (4)与本书相酉己套的互联网站点http：／／bwrc．eecs．berkeley．edu／IcBook／index．htm，为读者提供了大量的习题和其他实验资料。 |
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PrefacePart1TheFabricsChapter1Introduction1.1AHistoricalPerspective1.2IssuesinDigitalIntegratedCircuitDesign1.3QualityMetricsofaDigitalDesign1.3.1CostofanIntegratedCircuit1.3.2FunctionalityandRobustness1.3.3Performance1.3.4PowerandEnergyConsumption1.4Summary1.5ToProbeFurtherReferenceBooksReferencesChapter2TheManufacturingProcess2.1Introduction2.2ManufacturingCMOSIntegratedCircuits2.2.1TheSiliconWafer2.2.2Photolithography2.2.3SomeRecurringProcessSteps2.2.4SimplifiedCMOSProcessFlow2.3DesignRules-TheContractbetweenDesignerandProcessEngineer2.4PackagingIntegratedCircuits2.4.1PackageMaterials2.4.2InterconnectLevels2.4.3ThermalConsiderationsinPackaging2.5Perspective--TrendsinProcessTechnology2.5.1Short-TermDevelopments2.5.2IntheLongerTerm2.6Summary2.7ToProbeFurtherReferencesDesignMethodologyInsertAICLAYOUTA.1ToProbeFurtherReferencesChapter3TheDevices3.1Introduction3.2TheDiode3.2.1AFirstGlanceattheDiode--TheDepletionRegion3.2.2StaticBehavior3.2.3Dynamic,orTransient,Behavior3.2.4TheActualDiode--SecondaryEffects3.2.5TheSPICEDiodeModel3.3TheMOS(FET)Transistor3.3.1AFirstGlanceattheDevice3.3.2TheMOSTransistorunderStaticConditions3.3.3TheActualMOSTransistor---SomeSecondaryEffects3.3.4SPICEModelsfortheMOSTransistor3.4AWordonProcessVariations3.5Perspective--TechnologyScaling3.6Summary3.7ToProbeFurtherReferencesDesignMethodologyInsertBCircuitSimulationReferencesChapter4TheWire4.1Introduction4.2AFirstGlance4.3InterconnectParameters--Capacitance,Resistance,andInductance4.3.1Capacitance4.3.2Resistance4.3.3Inductance4.4ElectricalWireModels4.4.1TheIdealWire4.4.2TheLumpedModel4.4.3TheLumpedRCModel4.4.4TheDistributedrcLine4.4.5TheTransmissionLineSPICEWireModels4.5.1DistributedrcLinesinSPICE4.5.2TransmissionLineModelsinSPICE4.5.3Perspective:ALookintotheFuture4.6Summary4.7ToProbeFurtherReferencesPart2ACircuitPerspectiveChapter5TheCMOSInverter5.1Introduction5.2TheStaticCMOSInverter--AnIntuitivePerspective5.3EvaluatingtheRobustnessoftheCMOSInverter:TheStaticBehavior5.3.1SwitchingThreshold5.3.2NoiseMargins5.3.3RobustnessRevisited5.4PerformanceofCMOSInverter:TheDynamicBehavior5.4.1ComputingtheCapacitances5.4.2PropagationDelay:First-OrderAnalysis5.4.3PropagationDelayfromaDesignPerspective5.5Power,Energy,andEnergyDelay5.5.1DynamicPowerConsumption5.5.2StaticConsumption5.5.3PuttingItAllTogether5.5.4AnalyzingPowerConsumptionUsingSPICE5.6Perspective:TechnologyScalinganditsImpactontheInverterMetrics5.7Summary5.8ToProbeFurtherReferencesChapter6DesigningCombinationalLogicGatesinCMOS6.1Introduction6.2StaticCMOSDesign6.2.1ComplementaryCMOS6.2.2RatioedLogic6.2.3Pass-TransistorLogic6.3DynamicCMOSDesign6.3.1DynamicLogic:BasicPrinciples6.3.2SpeedandPowerDissipationofDynamicLogic6.3.3SignalIntegrityIssuesinDynamicDesign6.3.4CascadingDynamicGates6.4Perspectives6.4.1HowtoChooseaLogicStyle?6.4.2DesigningLogicforReducedSupplyVoltages6.5Summary6.6ToProbeFurtherReferencesDesignMethodologyInsertCHowtoSimulateComplexLogicCircuitsC.1RepresentingDigitalDataasaContinuousEntityC.2RepresentingDataasaDiscreteEntityC.3UsingHigher-LevelDataModelsReferencesDesignMethodologyInsertDLayoutTechniquesforComplexGatesChapter7DesigningSequentialLogicCircuits7.1Introduction7.1.1TimingMetricsforSequentialCircuits7.1.2ClassificationofMemoryElements7.2StaticLatchesandRegisters7.2.1TheBistabilityPrinciple7.2.2Multiplexer-BasedLatches7.2.3Master-SlaveEdge-TriggeredRegister7.2.4Low-VoltageStaticLatches7.2.5StaticSRFlip-FlopsWritingDatabyPureForce7.3DynamicLatchesandRegisters7.3.1DynamicTransmission-GateEdge-triggeredRegisters7.3.2C2MOS--AClock-SkewInsensitiveApproach7.3.3TrueSingle-PhaseClockedRegister(TSPCR)7.4AlternativeRegisterStyles*7.4.1PulseRegisters7.4.2Sense-Amplifier-BasedRegisters7.5Pipelining:AnApproachtoOptimizeSequentialCircuits7.5.1Latch-versusRegister-BasedPipelines7.5.2NORA-CMOS---ALogicStyleforPipelinedStructures7.6NonbistableSequentialCircuits7.6.1TheSchmittTrigger7.6.2MonostableSequentialCircuits7.6.3AstableCircuits7.7Perspective:ChoosingaClockingStrategy7.8Summary7.9ToProbeFurtherReferencesPart3ASystemPerspectiveChapter8ImplementationStrategiesforDigitalICS8.1Introduction8.2FromCustomtoSemicustomandStructured-ArrayDesignApproaches8.3CustomCircuitDesign8.4Cell-BasedDesignMethodology8.4.1StandardCell8.4.2CompiledCells8.4.3Macrocells,MegacellsandIntellectualProperty8.4.4SemicustomDesignFlow8.5Array-BasedImplementationApproaches8.5.1Prediffused(orMask-Programmable)Arrays8.5.2PrewiredArrays8.6PerspectiveTheImplementationPlatformoftheFuture8.7Summary8.8ToProbeFurtherReferencesDesignMethodologyInsertECharacterizingLogicandSequentialCellsReferencesDesignMethodologyInsertFDesignSynthesisReferencesChapter9CopingwithInterconnect9.1Introduction9.2CapacitiveParasitics9.2.1CapacitanceandReliability---CrossTalk9.2.2CapacitanceandPerformanceinCMOS9.3ResistiveParasitics9.3.1ResistanceandReliability--OhmicVoltageDrop9.3.2Electromigration9.3.3ResistanceandPerformance--RCDelay9.4InductiveParasitics*9.4.1InductanceandReliability--VoltageDrop9.4.2InductanceandPerformanceTransmission-lineEffects9.5AdvancedInterconnectTechniques9.5.1Reduced-SwingCircuits9.5.2Current-ModeTransmissionTechniques9.6Perspective:Networks-on-a-Chip9.7Summary9.8ToProbeFurtherReferencesChapter10TimingIssuesinDigitalCircuits10.1Introduction10.2TimingClassificationofDigitalSystems10.2.1SynchronousInterconnect10.2.2Mesochronousinterconnect10.2.3PlesiochronousInterconnect10.2.4AsynchronousInterconnect10.3SynchronousDesign--AnIn-depthPerspective10.3.1SynchronousTimingBasics10.3.2SourcesofSkewandJitter10.3.3Clock-DistributionTechniques10.3.4Latch-BasedClocking10.4Self-TimedCircuitDesign*10.4.1Self-TimedLogic--AnAsynchronousTechnique10.4.2Completion-SignalGeneration10.4.3Self-TimedSignaling10.4.4PracticalExamplesofSelf-TimedLogic10.5SynchronizersandArbiters*10.5.1Synchronizers---ConceptandImplementation10.5.2Arbiters10.6ClockSynthesisandSynchronizationUsingaPhase-LockedLoop*10.6.1BasicConcept10.6.2BuildingBlocksofaPLL10.7FutureDirectionsandPerspectives10.7.1DistributedClockingUsingDLLs10.7.2OpticalClockDistribution10.7.3SynchronousversusAsynchronousDesign10.8Summary10.9ToProbeFurtherReferencesDesignMethodologyInsertGDesignVerificationReferencesChapter11DesigningArithmeticBuildingBlocks11.1Introduction11.2DatapathsinDigitalProcessorArchitectures11.3TheAdder11.3.1TheBinaryAdder:Definitions11.3.2TheFullAdder:CircuitDesignConsiderations11.3.3TheBinaryAdder:LogicDesignConsiderations11.4TheMultiplier11.4.1TheMultiplier:Definitions11.4.2Partial-ProductGeneration11.4.3Partial-ProductAccumulation11.4.4FinalAddition11.4.5MultiplierSummary11.5TheShifter11.5.1BarrelShifter11.5.2LogarithmicShifter11.6OtherArithmeticOperators11.7PowerandSpeedTrade-offsinDatapathStructures*11.7.1DesignTimePower-ReductionTechniques11.7.2Run-TimePowerManagement11.7.3ReducingthePowerinStandby(orSleep)Mode11.8Perspective:DesignasaTrade-off11.9Summary11.10ToProbeFurtherReferencesChapter12DesigningMemoryandArrayStructures12.1Introduction12.1.1MemoryClassification12.1.2MemoryArchitecturesandBuildingBlocks12.2TheMemoryCore12.2.1Read-OnlyMemories12.2.2NonvolatileRead-WriteMemories12.2.3Read-WriteMemories(RAM)12.2.4Contents-AddressableorAssociativeMemory(CAM)12.3MemoryPeripheralCircuitry*12.3.1TheAddressDecoders12.3.2SenseAmplifiers12.3.3VoltageReferences12.3.4Drivers/Buffers12.3.5TimingandControl12.4MemoryReliabilityandYield*12.4.1Signal-to-NoiseRatio12.4.2MemoryYield12.5PowerDissipationinMemories*12.5.1SourcesofPowerDissipationinMemories12.5.2PartitioningoftheMemory12.5.3AddressingtheActivePowerDissipation12.5.4Data-RetentionDissipation12.5.5Summary12.6CaseStudiesinMemoryDesign12.6.1TheProgrammableLogicArray(PLA)12.6.2A4-MbitSRAM12.6.3A1-GbitNANDFlashMemory12.7Perspective:SemiconductorMemoryTrendsandEvolutions12.8Summary12.9ToProbeFurtherReferencesDesignMethodologyInsertHValidationandTestofManufacturedCircuitsH.1IntroductionH.2TestProcedureH.3DesignforTestabilityH.3.1IssuesinDesignforTestabilityH.3.2AdHocTestingH.3.3Scan-BasedTestH.3.4Boundary-ScanDesignH.3.5Built-inSelf-Test(BIST)H.4Test-PatternGenerationH.4.1FaultModelsH.4.2AutomaticTest-PatternGeneration(ATPG)H.4.3FaultSimulationH.5ToProbeFurtherReferencesProblemSolutionsIndexs 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